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1. general description the TEA5764HN is a single chip electronically tuned fm stereo radio with radio data system (rds) and radio broadcast data system (rbds) demodulator and rds/rbds decoder for portable application with fully integrated if selectivity and demodulation. the radio is completely adjustment free and only requires a minimum of small and low cost external components. the radio can tune to the european, us and japanese fm bands. it has a low power consumption and can operate at a low supply voltage. 2. features n high sensitivity due to integrated low noise rf input ampli?er n fm mixer for conversion of the us/europe (87.5 mhz to 108 mhz) and japanese fm band (76 mhz to 90 mhz) to if n preset tuning to receive japanese tv audio up to 108 mhz n auto search tuning, raster 100 khz n rf automatic gain control circuit n lc tuner oscillator operating with low cost ?xed chip inductors n fully integrated fm if selectivity n fully integrated fm demodulator; n no external discriminator n crystal oscillator at 32768 hz, or external reference frequency at 32768 hz n pll synthesizer tuning system n if counter; 7-bit output via the i 2 c-bus n level detector; 4-bit level information output via the i 2 c-bus n soft mute: signal dependent mute function n mono/stereo blend: gradual change from mono to stereo, depending on signal n adjustment-free stereo decoder n autonomous search tuning function n standby mode n mpx output n one software programmable port n fully integrated rds/rbds demodulator in accordance with en50067 n rds/rbds decoder with memory for two rds data blocks provides block synchronization and error correction; block data and status information are available via the i 2 c-bus n audio pause detector TEA5764HN fm radio + rds rev. 02 9 august 2005 product data sheet
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 2 of 64 philips semiconductors TEA5764HN fm radio + rds n interrupt ?ag 3. applications n fm stereo radio 4. quick reference data table 1: electrical parameters general the listed parameters are valid when a crystal is used that meets the requirements as stated in t ab le 47 ; all rf input values are de?ned in potential difference, except when emf is explicitly stated. symbol parameter conditions min typ max unit supplies v cca analog supply voltage 2.5 2.7 3.3 v i cca analog supply current v cca = 2.5 v to 3.3 v operating mode 12 13.7 16 ma standby mode 0 0.1 1 m a v ccd digital supply voltage 2.5 2.7 3.3 v i ccd digital supply current v ccd = 2.5 v to 3.3 v operating mode 0.3 0.7 1.5 ma standby mode 1 15 22.5 m a reference voltage v vrefdig digital reference voltage for i 2 c-bus interface 1.65 1.8 v ccd v i vrefdig digital reference supply current operating mode; v vrefdig = 1.65 v to v ccd 0 0.5 1 m a general f i(fm) fm input frequency 76 - 108 mhz t amb ambient temperature - 40 - +85 c fm and rds overall system parameters v sens(emf) sensitivity emf value voltage f rf = 76 mhz to 108 mhz; d f = 22.5 khz; f mod = 1 khz; (s+n)/n = 26 db; tc deem =75 m s; a-weighting ?lter; b aud = 300 hz to 15 khz - 2.3 3.5 m v ip3 in in-band 3rd-order intercept point d f 1 = 200 khz; d f 2 = 400 khz; f tune = 76 mhz to 108 mhz; rf agc = off 78 87 - db m v ip3 out out-of-band 3rd-order intercept point d f 1 = 4 mhz; d f 2 = 8 mhz; f tune = 76 mhz to 108 mhz; rf agc = off 87 93 - db m v s selectivity f tune = 76 mhz to 108 mhz [1] high-side; d f = +200 khz 39 43 - db low-side; d f = - 200 khz 32 36 - db v vafl left audio output voltage on pin vafl v rf = 1 mv; l = r; d f = 22.5 khz; f mod = 1 khz; no pre-emphasis; tc deem =75 m s 55 66 75 mv
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 3 of 64 philips semiconductors TEA5764HN fm radio + rds [1] low-side and high-side selectivity can be measured by changing the mixer lo injection from high-side to low-side. 5. ordering information v vafr right audio output voltage on pin vafr v rf = 1 mv; l = r; d f = 22.5 khz; f mod = 1 khz; no pre-emphasis; tc deem =75 m s 55 66 75 mv (s+n)/n(m) maximum signal-to-noise ratio, mono v rf = 1 mv; d f = 22.5 khz; l = r; f mod = 1 khz; de-emphasis = 75 m s; b af = 300 hz to 15 khz; a-weighting ?lter 54 57 - db (s+n)/n(s) maximum signal-to-noise ratio, stereo v rf = 1 mv; d f = 67.5 khz; l = r; f mod = 1 khz; d f pilot = 6.75 khz; de-emphasis = 75 m s; b af = 300 hz to 15 khz; a-weighting ?lter 50 54 - db a cs channel separation mst = 0; r = 1 and l = 0 or r = 0 and l = 1; v rf = 30 m v; increasing rf input level 27 33 - db thd total harmonic distortion v rf = 1 mv; d f = 75 khz; f mod = 1 khz; dtc = 0; b aud = 300 hz to 15 khz; a-weighting ?lter; mono; l = r; no pilot deviation - 0.4 0.9 % v sens rds sensitivity emf value d f = 22.5 khz; f af = 1 khz; l = r; sym1 = 0 and sym0 = 0; average over 2000 blocks; block quality rate 3 95 %; d f rds = 2 khz -1526 m v table 1: electrical parameters general the listed parameters are valid when a crystal is used that meets the requirements as stated in t ab le 47 ; all rf input values are de?ned in potential difference, except when emf is explicitly stated. symbol parameter conditions min typ max unit table 2: ordering information type number package name description version TEA5764HN hvqfn40 plastic thermal enhanced very thin quad ?at package; body 6 6 0.9 mm sot618-1
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 4 of 64 philips semiconductors TEA5764HN fm radio + rds 6. block diagram fig 1. block diagram 001aad315 2 if filter n1 i/q mixer 1st fm agc gain stabilizer crystal oscillator soft mute sds 19 i 2 c-bus interface mpx decoder tuning system mono pilot prog. div out i ref ref. div out mux sw port vco 18 16 15 12 w 3.7 w x1 10 k w 33 nf 33 nf 47 pf 27 pf l1 120 nh 100 pf 10 nf 12 pf 14 13 11 gndd intx intcon2 12 n.c. 17 n.c. 21 n.c. 22 23 24 25 26 intcon1 tmute vafr vafl mpxout mpxin gnda cd2/intcon3 v ccd gndd gndd sda busenable vrefdig scl 100 k w limiter level adc if center frequency adjust demodulator if count TEA5764HN 33 nf 33 nf 10 nf 29 n.c. n.c. gndd 27 28 30 32 31 n.c. 40 33 34 35 36 37 38 39 freqin xtal cd3 fm antenna rfin1 rfin2 gndrf cagc v cca 12 34 57 6 8 swport 9 10 loopsw cpout lo1 lo2 cd1 rds/rbds decoder 20 interface register 57 khz bp filter pause detector 33 nf 47 k w 33 nf 33 nf pillp l3 l3 d1 d2
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 5 of 64 philips semiconductors TEA5764HN fm radio + rds 7. pinning information 7.1 pinning 7.2 pin description fig 2. pin con?guration 001aab459 TEA5764HN n.c. vrefdig scl intcon1 busenable tmute swport vafr pillp vafl cd1 mpxout lo2 mpxin lo1 gndd cpout n.c. loopsw gnda sda n.c. gndd gndd v ccd cd2/intcon3 n.c. intcon2 gndd intx n.c. cagc gndrf rfin2 rfin1 cd3 v cca xtal freqin n.c. 10 21 9 22 8 23 7 24 6 25 5 26 4 27 3 28 2 29 1 30 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 terminal 1 index area transparent top view table 3: pin description symbol pin description loopsw 1 synthesizer pll loop ?lter switch output cpout 2 charge pump output of synthesizer pll lo1 3 local oscillator coil connection 1 lo2 4 local oscillator coil connection 2 cd1 5 vco supply decoupling capacitor pillp 6 pilot pll loop ?lter swport 7 software programmable port output busenable 8 i 2 c-bus enable input vrefdig 9 digital reference voltage for i 2 c-bus signals scl 10 i 2 c-bus clock line input sda 11 i 2 c-bus data line input and output n.c. 12 not connected gndd 13 digital ground gndd 14 digital ground v ccd 15 digital supply voltage cd2/intcon3 16 internally connected
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 6 of 64 philips semiconductors TEA5764HN fm radio + rds 8. functional description 8.1 low noise rf ampli?er the lna input impedance together with the lc rf input circuit de?nes an fm band ?lter. the gain of the lna is controlled by the rf agc circuit. 8.2 fm i/q mixer fm quadrature mixer converts fm rf (76 mhz to 108 mhz) to if. 8.3 vco the varactor tuned lc vco provides the local oscillator (lo) signal for the fm quadrature mixer. the vco frequency range is 150 mhz to 217 mhz. n.c. 17 not connected intcon2 18 internally connected; leave open gndd 19 digital ground intx 20 interrupt ?ag output n.c. 21 not connected intcon1 22 internally connected; leave open tmute 23 soft mute time-constant capacitor vafr 24 right audio output vafl 25 left audio output mpxout 26 fm demodulator mpx output mpxin 27 mpx decoder and rds decoder mpx input gndd 28 digital ground; this pin has an internal pull-down resistor of 10 k w to ground n.c. 29 not connected gnda 30 analog ground n.c. 31 not connected freqin 32 32.768 khz reference frequency input xtal 33 crystal oscillator input v cca 34 analog supply voltage cd3 35 v cca decoupling capacitor rfin1 36 rf input 1 rfin2 37 rf input 2 gndrf 38 rf ground cagc 39 rf agc time-constant capacitor n.c. 40 not connected table 3: pin description continued symbol pin description
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 7 of 64 philips semiconductors TEA5764HN fm radio + rds 8.4 crystal oscillator the crystal oscillator can operate with a 32.768 khz clock crystal. the oscillator can be overridden via the frefin pin. when the frefin pin is used the oscillator is clocked externally by a 32.768 khz signal. selection between a reference clock or a reference crystal can be done via the i 2 c-bus. when a crystal is connected the frefin pin must be left open-circuit, and when pin frefin is used a crystal may not be connected. it is not possible to connect a crystal and apply a frequency via the frefin pin in the same application. the crystal oscillator generates the reference frequency for the following: ? reference frequency divider for synthesizer pll ? timing for the if counter ? timing for the pause detector ? free running frequency adjustment of the stereo decoder vco ? centre frequency for adjustment of the if ?lters ? clock frequency of the rds/rbds decoder 8.5 pll tuning system the pll synthesizer tuning system is suitable to operate with a 32.768 khz reference frequency generated by the crystal oscillator or a reference clock of 32.768 khz fed into the TEA5764HN. to tune the radio to the required frequency requires the pll word to be calculated and then programmed to the register. the pll word is 14 bits long; see t ab le 20 and t ab le 21 . calculation of this 14-bit word can be done as follows. formula for high-side injection: (1) formula for low-side injection: (2) where: n dec = decimal value of pll word f rf = wanted tuning frequency (hz) f if = intermediate frequency of 225 khz f ref = the reference frequency of 32.768 khz example for receiving a channel at 100.1 mhz: (3) n dec 4f rf f if + () f ref -------------------------------------- = n dec 4f rf f if C () f ref ------------------------------------- - = n dec 4 100.1 10 6 225 10 3 + () 32768 ------------------------------------------------------------------------ 12246.704 ==
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 8 of 64 philips semiconductors TEA5764HN fm radio + rds the result found using equation 1 or equation 2 must always be rounded to the lowest integer value. if rounded down to the lowest integer value of n dec = 12246, the pll word becomes 2fd6h. this value can be written to register frqsetlsb or frqsetmsb via the i 2 c-bus and the ic will then either start an autonomous search at this frequency or go to a preset channel at this frequency. when the application is built according to the block diagram shown in figure 1 , and with the preferred components, the pll will settle to the new frequency within 5 ms. the most accurate tuning is accomplished when a search is followed by a preset to the same frequency. the pll is triggered by writing to any one of the bytes frqsetmsb, frqsetlsb, tnctrl1, tnctrl2, testbits, testmode. accurate validation of the pll locking on the new frequency can take 2 ms to 10 ms. when a lock is detected, bit ld is set. 8.6 band limits the TEA5764HN can be switched either to the japanese fm-band or to the us/europe fm-band. setting bit blim to logic 0 the band range is 87.5 mhz to 108 mhz; setting bit blim to logic 1 selects the japanese band range of 76 mhz to 90 mhz. 8.7 rf agc the rf agc (or wideband agc) prevents overloading and limits the amount of intermodulation products created by strong adjacent channels. the rf agc is on by default and can be turned off via the i 2 c-bus. the TEA5764HN also has an in-band agc to prevent overloading by the wanted channel. the in-band agc is always turned on. 8.8 local or long distance receive if bit ldx = 1, the lna gain is reduced by 6 db to prevent distortion when a transmitter is very near. if bit ldx = 0, the lna gain is normal to receive long distance (dx) stations. 8.9 if ?lter a fully integrated if ?lter is built-in. 8.10 fm demodulator the fm quadrature demodulator has an integrated resonator to perform the phase shift of the if signal. 8.11 if counter the received signal is mixed to produce an if of 225 khz. the result of the mixing is counted. a good if count result indicates that the radio is tuned to a valid channel instead of an image or a channel with much interference. the if counter outputs a 7-bit count result via the i 2 c-bus. the if counter is continuously active and can be read at any time via the i 2 c-bus. it also activates a ?ag when the if count result is outside the if count valid result window; see section 9.1.4.4 .
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 9 of 64 philips semiconductors TEA5764HN fm radio + rds before a tuning cycle is initiated the if count period can be set to 2 ms or to 15.6 ms by bit ifctc. when the if count period is set to 2 ms, initiating the tuning algorithm with a preset (bit sm = 0) will always give an rds update as shown in section 8.22.1 . in case the if count time is set to 15.6 ms, the tuning ?owchart illustrated in figure 3 is used. once tuned, the if count period is always 15.6 ms. 8.12 voltage level generator and analog-to-digital converter the voltage level indicates the ?eld strength received by the antenna. the voltage level is analog-to-digital converted to a 4-bit word and output via the i 2 c-bus. the adc level is continuously active and can be read at any time via the i 2 c-bus. it also activates a ?ag when the voltage level falls below a prede?ned selectable threshold. bit lhsw allows either large or small hysteresis steps to be chosen; see t ab le 24 and section 9.1.4.5 . when the adc level is set to 3, its minimum value, the search algorithm will only stop at channels having a rf level higher than, or equal to, adc level 3. after completing the search algorithm and being tuned to a station, due to hysteresis the effective limit will be set to 0. this means that the continuous adc level check will never set the levflag. 8.13 mute 8.13.1 soft mute the low-pass ?ltered voltage level drives the soft mute attenuator at low rf input levels: the audio output is faded and hence also the noise (see figure note 1 in figure 15 and figure 17 ). the soft mute function can also be switched off via the i 2 c-bus, using bit smute. 8.13.2 hard mute the audio outputs vafl and vafr can be hard-muted by bit mu in byte tnctrl2, which means that they are put into 3-state. this can also be done by setting bits left hard mute (lhm) or right hard mute (rhm) in byte testbits, which allows either one or both channels to be muted and forces the TEA5764HN to mono mode. when the TEA5764HN is in standby mode the audio outputs are hard-muted. 8.13.3 audio frequency mute the audio signal is muted by setting bit afm of the tnctrl1 register to logic 1. in the soft mute attenuator the audio signal is blocked and so pins vafl and vafr will be at their dc biasing point with no signal. the audio is automatically muted during an rds update as shown in the ?owchart of figure 3 . when the audio must be muted during search mode, it is done by setting bit afm to logic 1 before the search action and resetting it to logic 0 afterwards. setting bit afm to logic 0 stops the rds data. 8.14 mpx decoder the pll stereo decoder is adjustment free. it can be switched to mono via the i 2 c-bus.
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 10 of 64 philips semiconductors TEA5764HN fm radio + rds 8.15 signal dependent mono/stereo blend (stereo noise cancellation) if the rf input level decreases, the mpx decoder blends from stereo to mono to limit the output noise. the continuous mono-to-stereo blend can also be programmed via the i 2 c-bus to an rf level dependent switched mono-to-stereo transition. stereo noise cancellation can be switched off via the i 2 c-bus by bit snc. 8.16 software programmable port one software programmable port (cmos output) can be addressed via the i 2 c-bus: bit swpm = 1, the software port functions as the output for the frrflag. bit swpm = 0, the software port outputs bit swp of the registers. in test mode the software port outputs signals according to t ab le 27 . test mode is selected, setting bit tm of byte testmode to logic 1. the software port cannot be disabled by the pupd bits; see section 8.17 . 8.17 standby mode the radio can be put into standby mode by the power-up / power-down (pupd) bits. the rds part can be turned off separately or both the rds and the fm part can be turned off. the TEA5764HN is still accessible via the i 2 c-bus but takes only a low power from the supply, in standby mode, the audio outputs are hard-muted. 8.18 power-on reset after startup of v cca and v ccd a power-on reset circuit will generate a reset pulse and the registers will be set to their default values. the power-on reset is effectively generated by v ccd . after a power-on reset the TEA5764HN is in standby mode and the pupd bits are set to logic 0. after a power-on reset the registers are reset to their default value, except for byte12r to byte19r and ?ags davflg, lsyncflg and pdflag. to reset these, the rds part must be turned on by setting pupd. after setting pupd to logic 1, it will take 0.9 ms to start-up the TEA5764HN and set these registers to their default value. the power supplies can be switched on in any order. when the supply voltage v cca and v ccd are at 0 v, all i/os, the audio outputs and the reference clock input are high-ohmic. 8.19 rds/rbds 8.19.1 rds/rbds demodulator a fully integrated rds/rbds demodulator which uses the reference frequency (32.678 hz) of the pll synthesizer tuning system. the rds demodulator recovers and regenerates the continuously transmitted rds or rbds data stream of the multiplex signal (mpxrds) and provides the signals clock (rdcl), data (rdda) for further processing by the integrated rds decoder.
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 11 of 64 philips semiconductors TEA5764HN fm radio + rds 8.19.2 rds data and clock direct the rds demodulator retrieves the rds data and clock signals, this data can be put directly onto pins vafl and vafr by setting bit rdscda to logic 1. 8.19.2.1 rds/rbds decoder the rds decoder provides block synchronization, error correction and ?ywheel function for reliable extraction of rds or rbds block data. different modes of operation can be selected to ?t different application requirements. availability of new data is signalled by bit davflg and output pin intx which generates an interrupt. up to two blocks of data and status information are available via the i 2 c-bus in a single transmission. the behavior of the davflg is described in section 10 . 8.20 audio pause detector the audio pause detector monitors the audio modulation for pauses and responds to low levels. the modulation threshold can be adjusted in 4 steps of 4 db by control bits pl[1:0]. the minimum time for detecting a pause can be adjusted by control bits pt[1:0] as shown in t ab le 38 . when a pause occurs, ?ag pdflag is set to logic 1 and a hardware interrupt is generated; see section 9.1.4.6 . 8.21 auto search and preset mode in search mode the TEA5764HN can search channels automatically; see figure 3 .
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 12 of 64 philips semiconductors TEA5764HN fm radio + rds before starting a search or a preset, the intmsk register must be reset and only the frrmsk must be set. this allows the microprocessor to be interrupted only when the search or preset algorithm is ready. fig 3. flowchart auto search or preset 001aab461 during a preset mute is always active search mode is default not muted unless ahlsi is set blflag = 0 frrflag = 1 no mute reset flags set pll frequency increment current_pll by 100 khz decrement current_pll by 100 khz wait for pll to settle set levflag true false level ok start true false if ok true false ahlsi false search up true true false band limit true false search mode blflag = 0 frrflag = 1 mute blflag = 1 frrflag = 1 no mute
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 13 of 64 philips semiconductors TEA5764HN fm radio + rds 8.21.1 search mode search mode is initiated by setting bit sm in byte frqsetmsb to logic 1. the search direction is set by bit sud; sud = 0 (search down), bit sud = 1 (search up). the tuner starts searching at the frequency set in bytes frqsetlsb and frqsetmsb. the search stop level (ssl) bits de?ne the ?eld strength level at which a desired channel is detected. the tuner will stop on a channel with a ?eld strength equal to or higher than this reference level and then checks the if frequency; when both are valid, the search stops (note that this depends on bit ahlsi described in figure 3 ). if the level check or the if count fails, the search continues. if no channels are found, the TEA5764HN stops searching when it has reached the band limit, setting the blflag high. a search always stops when the frrflag is set and on the occurrence of a hardware interrupt, this procedure is shown in figure 3 . the search algorithm can stop at a frequency that is offset from the if by up to a maximum of 12 khz. the maximum offset can be limited to 8 khz by applying a preset. for optimum tuning, it is recommended that a preset is applied after a search and when the found frequency has an offset that is above 8 khz. after this interrupt the TEA5764HN will not update the tuner registers for a period of 15 ms. the state of the TEA5764HN can be checked by reading the bytes of intflag, frqchkmsb, frqchklsb, tnctrl1 and tnctrl2. t ab le 4 shows the possible states of these registers after an auto search. [1] this table is valid until 30.6 ms after the tuning cycle has completed. it shows the outcome of the ?ag register when a read is done after pin intx goes low on condition that no mask bit other than frrmsk is set. 8.21.2 preset mode a preset occurs by setting bit sm to logic 0 and writing a frequency to byte frqsetmsb. the tuner jumps to the selected frequency and sets the frrflag when it is ready. after this interrupt the TEA5764HN will not update the tuner registers for a period of 15 ms. the state of the TEA5764HN can be checked by reading registers: intflag, frqchklsb, frqchkmsb, tnctrl1 and tnctrl2. t ab le 4 shows the possible states after a preset. table 4: tuner truth table [1] ifflag blflag frrflag comment 0 0 0 if pin intx has gone low and only ifmsk, frrmsk and blmsk were set then this cannot occur 0 0 1 channel found during search / preset; frrmsk set 0 1 0 not a valid state 0 1 1 a valid channel found and the band limit has been reached during a search; blmsk or frrmsk set 1 0 0 not a valid state 1 0 1 a preset or search has occurred but the wanted channel has a valid rssi level but fails the if count when ahlsi was set to logic 1; hlsi must be toggled and a new pll value must be programmed; frrmsk set 1 1 0 not a valid state 1 1 1 band limit is reached during search; no valid channel found; blmsk or frrmsk set
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 14 of 64 philips semiconductors TEA5764HN fm radio + rds 8.21.3 auto high-side and low-side injection stop switch when a channel is searched or a preset is done, reception can sometimes improve when injection is done at the other side of the wanted channel. the TEA5764HN has bit hlsi which toggles the injection of the local oscillator from high-side (bit hlsi = 1) to low-side (bit hlsi = 0). when bit hlsi is toggled, a new pll setting must be sent to the TEA5764HN. when bit ahlsi is set to logic 1, the search / preset algorithm will stop after a channel has a valid rssi level check but fails the if count. the microprocessor can now respond by toggling the hlsi switch and sending a new pll value to the tuner. 8.21.4 muting during search or preset during a preset the tuner is always muted and this is implemented by the algorithm. a search is not muted by default unless bit afm = 1 or bit ahlsi = 1. when bit ahlsi = 1 and the tuner stopped during a preset or a search because of a wrong if count, the tuner stays muted; this allows the microprocessor to switch from the high to low setting quietly and wait for the new result. the tuner is always muted if bit afm = 1 and is independent of a search or a preset. a search can be muted by setting bit afm to logic 1 before a search is initiated and resetting it to logic 0 when the tuner is ready (only set bit frrmsk when initiating a search or preset). all these mute actions are done by blocking the audio signal inside the soft mute attenuator, the audio output will keep its dc level and stay low-ohmic i.e. 50 w (a hard mute set by bit mu will cause a plop). 8.22 rds update/alternative frequency jump a channel which transmits rds data can have alternative channels which have the same information. these alternative channel frequencies are in the rds data, so the microprocessor can read the alternative frequencies and store them in a memory. the tuner can perform an rds update. this is very similar to a preset, but with a 2 ms if count time. the tuner will jump to the alternative frequency and check the level and the if count using a 2 ms count time. when the rssi level check is above the speci?ed level and the if count result is within the limits, then the tuner will stay at the alternative frequency and stay muted, the microprocessor can now decide what to do. if the alternative frequency is not valid it will jump back to the frequency it came from. fig 4. switch lo from high-side injection to low-side injection using bit hlsi 001aab460 image on high-side wanted channel switch lo from high-side to low-side image on low-side
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 15 of 64 philips semiconductors TEA5764HN fm radio + rds the algorithm will ?nish with the frrflag being set and an interrupt is generated. after this interrupt the TEA5764HN will not measure the if count for a period of 15 ms. 15 ms after completing a rds jump, a measurement of the if count will start and hence the if count result and the ifflag will be updated 30.6 ms after completing the algorithm. the level measurement will start immediately after the tuning algorithm, so the levflag will be updated 500 m s after the algorithm. the state of the TEA5764HN can be checked by reading registers intflag, frqchklsb, frqchkmsb, ifchk and levchk. t ab le 5 shows the possible states after an auto search, figure 5 shows how the rds is updated. 8.22.1 muting during rds update an rds update (af jump) is always muted. there are two possibilities for leaving the algorithm: ? the tuner jumps to an alternative frequency which is not valid (according to the speci?ed ssl limit and ?xed if counter limits) and jumps back, then it will automatically unmute ? or the tuner jumps to a valid alternative frequency and stays there. now it does not unmute. the microprocessor can unmute or it keeps the tuner muted and can check for the presence of rds data. the valid way to unmute is to apply a preset to the current frequency (an if count time of 15.6 ms is used at preset, which gives a more accurate if count result than the result obtained by the af jump, where 2 ms is used) [1] this table is valid until 30.6 ms after an rds update has completed. it shows the outcome of the ?ag register when a read is done after pin intx has gone low and on condition that only mask bit frrmsk is set. table 5: rds update truth table [1] ifflag blflag frrflag comment 0 0 0 if pin intx is low and only ifmsk, frrmsk and blmsk were set then this cannot occur 0 0 1 alternative frequency jump successful; radio is tuned to the alternative frequency and stays muted 0 1 0 not a valid state 0 1 1 not a valid state 1 0 0 not a valid state 1 0 1 af jump has occurred but the wanted channel fails the if count; the pll will be set back to the old value 1 1 0 not a valid state 1 1 1 if pin intx is low and only ifmsk, frrmsk and blmsk were set then this cannot occur
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 16 of 64 philips semiconductors TEA5764HN fm radio + rds 9. interrupt handling 9.1 interrupt register the ?rst two bytes of the i 2 c-bus register contain the interrupt masks and the interrupt ?ags. a ?ag is set when it is a logic 1. fig 5. flowchart rds update 001aab462 activate mute store 'old' pll setting clear levflag clear ifflag set pll to af frequency frrflag = 1 blflag = 0 keep mute (pll is af frequency) frrflag = 1 blflag = 0 not mute (pll is old frequency) wait for pll to settle set levflag true false level ok wait for if counter reset 'old' pll setting false true if ok wait for pll to settle start set if count time to 2 ms table 6: intflag - byte0r bit 7 6 5 4 3 2 1 0 symbol davflg testbit lsyncflg ifflag levflag pdflag frrflag blflag table 7: intmsk - byte0w / byte1r bit 7 6 5 4 3 2 1 0 symbol davmsk - lsyncmsk ifmsk levmsk pdmsk frrmsk blmsk
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 17 of 64 philips semiconductors TEA5764HN fm radio + rds the interrupt ?ag register contains the ?ags set according to the behavior outlined in section 9.1.4 . when these ?ags are set they can also cause the intx to go active (hardware interrupt line) depending on the status of the corresponding mask bit in t ab le 7 . a logic 1 in the mask register enables the hardware interrupt for that ?ag. hence, it is conceivable that, with all the mask bits cleared, the software could operate in a continuous polling mode that reads the interrupt ?ag register for any bits that maybe set. interrupt mask bits are always cleared after reading the ?rst two bytes of the interrupt register. this is to control multiple hardware interrupts (see figure 6 ). bit lsyncmsk has a different function and is not cleared after reading the interrupt register bytes; see also section 9.1.4.3 . 9.1.1 interrupt clearing the interrupt ?ag and mask bits are always cleared after: ? they have been read via the i 2 c-bus ? a power-on reset 9.1.2 timing the timing sequence for the general operation interrupts is shown in figure 6 and shows a read access of the interrupt bytes intflag and intmsk and a subsequent (though not necessarily immediate) write to the mask register. it also indicates the two key timing points a and b. if an interrupt event occurs while the register is being accessed (after point a) it must be held until after the mask register is cleared at the end of the read operation (point b). point a is after the r/w bit has been decoded and point b is where the acknowledge has been received from the master after the ?rst two bytes have been sent. the low time for the intx line (t low ) has a maximum value speci?ed in section 15 . however it can be shorter if the read of the intmsk and intflag bytes occurs within t low . 9.1.3 reset a reset can be performed at any time by a simple read of the interrupt bytes, byte0r and byte0w, which automatically clears the interrupt ?ags and masks.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 18 of 64 philips semiconductors TEA5764HN fm radio + rds (1) interrupt events that occur outside of the region a-b set their respective ?ag bits in the normal way immediately and can th us trigger a hardware interrupt if the mask bits are set. (2) the blocking of interrupts is marked by the region a-b 1 / b 2 depending on the actual read cycle. b 1 is when only the intflag is read and a stop condition is received (only intflag is read so only this will be cleared). b 2 is when both registers are read and hence cleared and this is terminated by either an acknowledge or stop bit. (3) interrupt events that occur between a and b set their respective ?ags after the mask bits are cleared. which means that in this diagram an interrupt e vent occurred in period a-b, so after a-b the ?ag goes to logic 1. (4) all interrupt mask bits are cleared after the interrupt ?ag and mask bytes are read. (5) software writes to the mask byte and enables the required mask bits. any ?ags currently set will then trigger a hardware int errupt. (6) intx is set high (inactive) after the interrupt mask bytes are read. fig 6. i 2 c-bus interrupt sequence, read and write operation 001aab464 device address intflag intmsk read access data intmsk frqsetmsb frqsetlsb write access sr a interrupt event interrupt flag bit 0r data a a (1) (2) (3) interrupt mask bit (4) (5) (6) (5) b 1 b 2 1r data a data a device address s p w a 0w data a 1w data a 2w data a intx
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 19 of 64 philips semiconductors TEA5764HN fm radio + rds 9.1.4 interrupt ?ags and behavior 9.1.4.1 multiple interrupt events if the interrupt mask register bit is set then the setting of an interrupt ?ag for that bit causes a hardware interrupt (pin intx goes low). if the event occurs again, before the ?ag is cleared, then this does not trigger any further hardware interrupts until that speci?c ?ag is cleared. however, two different events can occur in sequence and generate a sequence of hardware interrupts. a second interrupt can be generated only after the intmsk byte is read, followed by a write as the ?rst interrupt blocks the input of the intx one-shot generator. if subsequent interrupts occur within the intx low period then these do not cause the intx period to extend beyond its speci?ed maximum period (see section 9.2 ). 9.1.4.2 data available ?ag the davflg is set when a new block of data is received according to figure 9 to figure 12 , where the different dav modes are described. once synchronized, this continues for all subsequent received blocks (dependent on dav mode) and in the following situations: ? during sync search, in any dav mode: two valid blocks in the correct sequence received with bbc < bbl (synchronized). ? during synchronization search in davb mode if a valid a(c)-block has been detected. this mode can be used for fast search tuning (detection and comparison of the pi code contained in the a or c block. ? if the pre-processor is synchronized and in mode dava and davb a new block has been processed. this mode is the standard data processing mode if the decoder is synchronized. ? if the pre-processor is synchronized and in davc mode, two new blocks have been processed. ? if the decoder is synchronized and in any dav mode, with lsyncmsk = 0, loss of synchronization is detected (?ywheel loss of synchronization, resulting in a restart of synchronization search). the davflg is reset by a read of rdslblsb (byte15r) or rdspblsb (byte17r). an interrupt is asserted each time a new block of data is decoded and when bit davmsk is set; see section 10 . 9.1.4.3 rds synchronization ?ag bit sync, t ab le 29 , shows the status of the rds decoder. if it is a logic 1 then the decoder is synchronized, if it is a logic 0 it is not. the action of the TEA5764HN depends on the status of bit lsyncmsk in t ab le 7 . if this is set then the loss of synchronization causes bit lsyncfl to go to logic 1 when synchronization is lost, and a hardware interrupt is asserted. the rds part of the TEA5764HN is set to idle and waits for the microprocessor to initiate a new synchronization search by setting bit nwsy as described in t ab le 36 .
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 20 of 64 philips semiconductors TEA5764HN fm radio + rds if bit lsyncmsk is 0 and synchronization is lost, the asic automatically starts a new synchronization search. it will not generate a hardware interrupt. the microprocessor can wait until the rds decoder is synchronized again, this will be indicated by the davflg and the sync status bit (this requires bit davmsk being set). bit lsyncfl is reset by a read of the intmsk byte1r. bit lsyncmsk is not reset by a read of byte intmsk, it must be set or reset by the microprocessor. resetting it automatically would change the status of the asic and cause an automatic synchronization search as described above. how the synchronization is de?ned is explained in brief in section 10 . 9.1.4.4 if frequency ?ag during an automatic frequency search, preset or af update, the fm part of the TEA5764HN performs a check of the received if frequency as a measure of the level of interference in the channel received. if an incorrect if frequency is received, it indicates the presence of either strong interferers or tuning to an image which sets bit ifflag in the intflag register. also a preset to a channel with no signal will result in a wrong if count value and hence the setting of bit ifflag. when a search, preset or af update is ?nished, bit frrflag will be set to indicate this and will generate an interrupt. the microprocessor can now read the outcome of the registers which will contain the if count value and the ifflag status of the channel it is tuned to. in the case of an af update, the if count value of the alternative frequency will be in the registers and also when it jumps back, because it will then not start a new if count. 15 ms after the tuning algorithm has completed the if counter will start a new count. so 30.6 ms after a failed af update the if count result will be equal again to that of the channel from where the jump was initiated. 15 ms after the frrflag has been set the if counter will start to run continuously on the tuned frequency and if the conditions for correct frequency are not met then this sets bit ifflag in the interrupt register. when bit ifmsk is set this will also cause an interrupt. bit ifflag is cleared by a read of byte1r, or by starting the tuning algorithm. 9.1.4.5 rssi threshold ?ag the voltage level re?ects the ?eld strength received by the antenna. the voltage level is analog to digital converted to a 4-bit value and output via the i 2 c-bus, this 4-bit level value can be compared to a threshold level set by the ssl bits in t ab le 19 or the lh bits in t ab le 26 . the adc level (which converts the analog value to digital) can be triggered to convert in either of two ways: 1. during a tuning step, a search, a preset or an af update, it is triggered by these algorithms and compares the level with the threshold set by bits ssl[1:0]. bit levflag is set if the rssi level drops below the threshold level set by bits ssl[1:0]; see t ab le 19 . the hardware interrupt is only generated if the corresponding mask bit is set.
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 21 of 64 philips semiconductors TEA5764HN fm radio + rds 2. after a search, a preset or an af update, the threshold for comparison is switched to the hysteresis level. the hysteresis level is set by the combination of bits ssl[1:0] and bit lhsw; see t ab le 24 . the result is a hysteresis as shown in t ab le 26 . then the adc level starts to run automatically and compares the level every 500 m s with the hysteresis level. bit levflag is set if the rssi level drops below the threshold level set by bits ssl[1:0] in combination with bit lhsw (see t ab le 26 ); the hardware interrupt is only generated if the corresponding mask bit is set. bit lhsw allows either a small or a large hysteresis to be selected which results in the levels of the left rssi hysteresis threshold column for bit lhsw = 0 and the right rssi hysteresis threshold column; see t ab le 26 . when a search or preset is done with the adc level set to 3 then when the algorithm has ?nished, the threshold level is set to 0. hence the levflag will never be set. bit levflag is cleared by a read of the intmsk byte1r, or by starting the tuning algorithm. 9.1.4.6 pause detection ?ag the pause detector monitors the amplitude of the audio signal and starts counting if it drops below the reference level. when the counter reaches the speci?ed count time, a pause is detected and the pdflag is set and will generate an interrupt if bit pdmsk is set to logic 1. the pdflag operates independently of bit pdmsk and is only active when the rds decoder is switched on when bit pupd is set to logic 1 and when the rds decoder is not idle if synchronization is lost. see figure 7 . when the peak audio level of the (l+r) drops below the threshold level at t 1 it counts the duration of the pause. if the pause lasts longer than the value set by the pt bits, bit pdflag is set which in turn generates a hardware interrupt (bit pdmsk set to logic 1). the threshold level at t 1 is set by the pl bits shown in t ab le 38 . bit pdflag is cleared by a read of byte1r on condition that the read action occurs more than 500 m s after receiving the pause interrupt on the intx line. the circuit should ignore short transients where the audio level momentarily rises above the threshold (at t 2 ). a pause is detected by comparing the amplitude of the audio signal with the reference level selected by the pl bits. the resultant signal psco produced by this comparison is sampled at a frequency of 2341 hz resulting in signal pscon. a pause is detected under the conditions given by equation 4 and equation 5 . (4) (5) where n is the number of samples taken over time and pt is the pause time selected by bus bits pt. when a pause is detected, the integrator will be reset. the integrator value cannot be less than zero; therefore if in equation 4 , the value of the second sum becomes larger than the ?rst sum, the output of the integrator remains at zero. suppose that pt = 20 ms, t pause = 16 ms and t audio = 1.5 ms. the pause detector will count according to equation 5 as shown in equation 6 : (6) sum 0ton 1 C () pscon 0 = [] 8 sum 0ton 1 C () pscon 1 = [] C {} pt 2341 > t pause 8t audio pt > C 2t pause 8t C audio 20 ms 2 16 ms 8 1.5 ms C 3 20 ms ==
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 22 of 64 philips semiconductors TEA5764HN fm radio + rds in equation 6 , the pause detector has measured 1 16 ms pause, 8 1.5 ms no pause and 1 16 ms pause. therefore on average the pause detector has measured 16 ms - 12 ms + 16 ms = 20 ms pause time and hence a pause will be detected. the pscon signal goes directly to the software port. the pdflag is set by the integrator and goes to the bus. the interrupt line is triggered by the pdflag. 9.1.4.7 frequency ready ?ag the frequency ready ?ag bit is set to logic 1 when the automatic tuning has ?nished a search, a preset or an rds af update. this bit is described in t ab le 4 and t ab le 5 . the frrflag is cleared by a read of byte1r. t np(min) > 5 ms. (1) the reference level is de?ned in khz, but is internally transformed to mv e.g. 22.5 khz = 75 mv; 1 khz = 3.3 mv. (2) the actual psco signal behaves as shown in the top diagram, in the bottom diagram it is assumed that all samples are taken at peaks of the audio signal resulting in pscon. fig 7. operation and timing of pause detection according to levels set in t ab le 38 001aac795 audio signal psco audio 0 (2) no audio present audio present pt x 2341 + reference level "pl" [mv] (1) pause no pause - reference level "pl" 0 pscon t pause t audio t pause pdflag integrator output t 1 t 2
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 23 of 64 philips semiconductors TEA5764HN fm radio + rds 9.1.4.8 band limit ?ag the band limit bit blflag is set to logic 1 when the automatic tuning has detected the end of the tuning band or when the pll cannot lock on a certain frequency. this bit is described in t ab le 4 and t ab le 5 . this bit is cleared by reading byte1r. 9.2 interrupt output the interrupt line driver is a mos transistor with a nominal sink current of 680 m a, it is pulled high by an 18 k w resistor connected to pin vrefdig. the interrupt line can be connected to one other similar device with an interrupt output and an 18 k w pull-up resistor providing a wired or function. this allows any of the drivers to pull the line low by sinking the current. when a ?ag is set and not masked it generates an interrupt; see figure 8 . 10. rds data processing the rds demodulator and decoder perform the following operations: ? demodulation of the rds/rdbs data stream from the mpx signal ? symbol decoding ? block and group synchronization ? error detection and correction ? store last and previous data block received with associated id and error status ? set the davflg when new data is received ? set the sync status bit according to the current synchronization state ? set the lsyncfl ?ag when synchronization is lost the rds decoder can be set to different modes, each meant to look for speci?c information. read intmsk clears ?ag, intmsk and intx. write intmsk enables intx. when ?ag is set, the next interrupts are blocked until read / write intmsk. (1) flag is set immediately after the reset, because event is still there. fig 8. interrupt line behavior 001aab470 v cca flag intx read intmsk 10 ms < 10 ms read clears intx (1) write intmsk 10 ms < 10 ms
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 24 of 64 philips semiconductors TEA5764HN fm radio + rds 10.1 dav-a processing mode the dav-a processing mode is the standard processing mode used. in this mode, when a data block has been decoded, it is transferred to the i 2 c-bus registers. it generates interrupts on the intx line after every new block of rds data that has been processed and also sets the davflg; see figure 9 . the davflg is reset by a read of the i 2 c-bus registers. if a data block is decoded and a new one arrives, pin intx goes low again, the davflg will be set and the last block will be shifted to the previous block and the last decoded block will be put in the last block. this means that all rds data is still available in the bl and bp registers. when the i 2 c-bus registers are not read the davflg will not be reset. if a data block is decoded and a new one arrives, pin intx goes low and the last block will be shifted to the previous block and the last decoded block will be put in the last block. this means that all rds data is still available in the bl and bp registers but must be read. this is indicated by the setting of bit dovf. if the i 2 c-bus registers are still not read, data will be lost, except when this read is done within 20 ms after the intx line has gone low and 2 ms before the arrival of a new block. if this read is done at least 2 ms before the arrival of a new block, then bl and bp are read and the data in the decoder buffer is then instantaneously shifted to the bl register. all data is now read and bit dovf will be reset.
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 25 of 64 philips semiconductors TEA5764HN fm radio + rds figure 9 assumes that block synchronization has been achieved and that no other interrupt ?ags are being set. 10.2 dav-b processing mode / fast pi search mode this mode is used, for example, when the receiver has been re-tuned to a new station, and a fast search of the pi code, always contained in the a or c block, is required. the diagram shown in figure 10 , assumes that the rds decoder is unsynchronized initially and is performing a synchronization search. during synchronization search the decoder does not set the davflg until a valid a or c block is detected. if a valid b block is detected immediately, then the decoder is now synchronized and bit sync is set to logic 1. in fact, if any 2 good blocks in a valid order are detected, the rds decoder will synchronize and give an interrupt. bit dovf set when 2 new blocks received in bl and bp registers (1) if there is no read cycle, b 1 is placed in the bp register and the new block c 1 is now in the bl register. bit dovf is set to indicate two blocks available. (2) data is not transferred to bl register at the end of the read period/clear dovf, d 1 is missed. (3) in order not to lose d 1 a read must be performed before d 1 enters decoder buffer, thus read ?nishes within 21 ms after dovf set to logic 1. (4) dovf is cleared when the bl register is read. to be of use, dovf has to be read before bl and bp registers. (5) to prevent dovf being set again, an extra read of bl must be performed before a2 has been decoded. fig 9. dav-a timing diagram, dav-a/b: normal 001aab471 a 1 21.9 ms davflg davflg set on falling edge davn = 0, cleared on read bl register intx b 1 read bl end read intmsk read intflg + rds on intx t int_rd t read bl register a 1 bp register t int_rd < ? 10 ms read bl read bl c 1 d 1 a 2 b 2 c 2 b 1 (1) (3) (2) (4) (2) (1) (5) c 1 d 1 b 2 xa 1 b 1 c 1 a 2 being decoded b 1 in the decoder buffer data overflow bit c 1 d 1 a 2 a 1 b 1 c 1 d 1 c 1 b 1 a 2 d 1 a 2 d 1 a 2 a 2 b 2 a 2 b 2 a 1 decoder registers: 9.98 ms 9.98 ms > 2 ms
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 26 of 64 philips semiconductors TEA5764HN fm radio + rds if for some reason a valid b block was not received then the next valid a or c block is decoded and the davflg set. the bp and bl registers record the a block history. when the decoder is synchronized, each decoded block will set the davflg (assuming it was reset by a read action) and generate an interrupt. 10.3 dav-c reduced processing mode the dav-c processing mode is very similar to dav-a mode with the main exception that a data ?ag is set only after two new blocks are received. hence the update rate is reduced by half. when the number of blocks detected in the order: bad bad good is 2, synchronization is achieved if another good block followed by either 0, 1 or 2 bad blocks and another good block are then received. if the order is 3 bad blocks, no synchronization is achieved and the counters are reset. fig 10. dav-a timing diagram, dav b: with bad blocks detected during sync search 001aab472 b 1 21.9 ms only valid blocks with no errors are counted as good blocks error correction applied according to sym bits bad good good good bad read bl register read intmsk not synchronized synchronized davflg intx sync status bit good a or c' block detected bad c' 1 bus access - read d 1 a 2 b 2 c 2 bl register x bp register c' 1 c' 1 c' 1 b 2 c 2 xxxxc' 1 b 2
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 27 of 64 philips semiconductors TEA5764HN fm radio + rds fig 11. normal dav-c timing diagram fig 12. dav-c timing diagram, late read of bl, bp register 001aab473 a 1 21.9 ms b 1 davflg cleared at end read bp register and forced to zero till end read of rds 4r bl register copied to bp register and c 1 to bl register b 1 copied to bl register shortly before c 1 decoded intx cleared at end read intmsk t intx t int_rd t read davflg being decoded read access (case 1) intx c 1 d 1 a 2 b 2 001aab474 a 1 21.9 ms b 1 davflg reset when 1 st new block would have been copied davflg set when 2 nd new block in decoder buffer instant copy of a 2 from decoder buffer to bl, and bl to bp instant copy c 1 from decoder buffer to bl, and bl to bp just before d 1 decoded due to read action (a) davflg not cleared as no read performed t read t intx = 10 ms intx read access (case 2) data overflow bit no read on intx so b 1 will be lost 2 new blocks have arrived in bl/bp (c 1 , d 1 ) and a new block (a 2 ) has entered the decoder buffer. hence, dovf is set again. to prevent this, an extra read must be performed after reading (a) dashed line shows what would happen if no read occurred at (a). dovf bit set until the next read of bp register, however d1, a2 would be lost c 1 d 1 a 2 b 2 bl register a 1 bp register d 1 c 1 a 2 d 0 d 0 c 0 c 1 a 1 d 1 davflg (case 2)
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 28 of 64 philips semiconductors TEA5764HN fm radio + rds 10.4 synchronization 10.4.1 conditions for synchronization when the rds decoder is turned on it must be synchronized to extract valid data from the mpx signal. to do so the decoder automatically initiates a search for synchronization. the conditions to meet synchronization and the status of this synchronization can be set and checked by the following bits: ? bbl (bad blocks lose): these bits can be set via the i 2 c-bus and have a value between 0 to 63 ? gbl (good blocks lose): these bits can be set via the i 2 c-bus and have a value between 0 to 63 ? bbg (bad blocks gain): these bits can be set via the i 2 c-bus and have a value between 0 to 32 ? gbc (good block count): these bits can be read via the i 2 c-bus and have a value between 0 to 63 ? bbc (bad block count): these bits can be read via the i 2 c-bus and have a value between 0 to 63 when the decoder is not synchronized it will initiate a synchronization search. this involves calculation of the syndrome for each block of 26 received bits on a bit-by-bit basis. when a correct syndrome (and hence block id) is received the decoder clocks the next 26 bits into the internal registers and performs a second syndrome check. synchronization is found when a certain number of blocks have been decoded and two good blocks have been found, this number of blocks is de?ned by the bbg bits. if the ?rst block needed for synchronization has been found and the expected second block (after 26 bits) is an invalid block, then the decoder module internal bad_blocks_counter is incremented and the next expected block is calculated; exception: if rbds mode is selected and the ?rst block is e, then the next expected block is always block a, until synchronization is found or the maximum bad_blocks_counter value is reached. if the decoder module internal bad_blocks_counter reaches the value of bbg[4:0], then a new synchronization search (bit-by-bit) is started immediately to ?nd a new ?rst block. the synchronization is monitored by two ?ywheel counters, gbc and bbc. these are 6-bit counters that can be preset by bits gbl and bbl to values between 0 and 63. each time a block is decoded and recognized as a bad block the bad block counter value, bbc, is incremented by 1. when the bbc value is equal to the bbl value, synchronization is lost. bit sync will become 0 and bit lsyncfl is set to indicate the loss of synchronization. the TEA5764HN will now automatically initiate a new synchronization search. each time a good block is decoded, the gbc value is incremented. when the gbc value is equal to the gbl value, both counters, bbc and gbc, are set to 0 and a new count starts. the gbc counter is only incremented when the decoder is synchronized.
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 29 of 64 philips semiconductors TEA5764HN fm radio + rds 10.4.2 data over?ow during synchronization, after rds data is read from the registers, new available blocks are shifted to the registers as described in section 10.1 to section 10.3 . if the registers are not read in time, the decoder cannot shift any new available block to the registers and hence a data over?ow will occur, this is indicated by bit dovf which is set to 1. bit dovf is reset by a read of the registers or if bit nwsy = 1 which results in the start of a new synchronization search. each time when a rds data block is decoded, bit davn goes to logic 0 to indicate the presence of a new data block. bit davn also triggers the interrupt output intx. in principle the microprocessor must now start reading and must have read all rds data (byte12r to byte19r) before the arrival of a new rds data block. in the application it is possible that there is too large a delay between the arrival of a new block and reading this block. this can have various causes such as a microprocessor that has to start-up from sleep mode or when polling is used instead of interrupt based read actions. figure 13 shows the behavior of bit davflg and bit davn when polling, where reading can occur at any time. note: bit davn sets the intx oneshot generator when davmsk = 1. unlike intx, bit davn is not cleared by a read of the mask register.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 30 of 64 philips semiconductors TEA5764HN fm radio + rds 10.5 rds ?ag behavior during read action blocking davflg: at end of reading byte15r or byte17r (dav-a, b/c) davflg is forced to zero. only after reading byte19r davflg is released again. if synchronous reading is performed using asic generated interrupts, this problem does not occur. to prevent unde?ned situations, byte12r to byte19r should always be read in one action immediately after each other. signal davn 1 intx. (1) normally reading byte19r would reset bit davn, but now it is reset after 10 ms, the maximal low time of bit davn. (2) read of byte15r in dav-a and dav-b mode clears davflg. in dav-c mode two consecutive rds data blocks are read and hence davf lg is reset after reading byte17r instead of byte15r (dotted line). (3) read of byte19r clears bit davn. (4) write byte0w (interrupt register). fig 13. rds ?ag behavior b a rds data davn davflg reset of davflg read byte: 15r 0r 19r 0w 17r cda b (1) (2) (3) (4) 10 ms c 15r 0r 19r 0w 17r 15r 0r 19r 0w 17r 15r 0r 19r 0w 17r 15r 0r 19r 0w 17r 15r 0r 19r 0w 17r 001aab475
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 31 of 64 philips semiconductors TEA5764HN fm radio + rds 10.6 error detection and reporting the tda5764hn must report information on the number of errors corrected in the last and previously decoded blocks. this is reported in bits elb and epb as shown in t ab le 29 . during synchronization search the error correction is disabled for detection of the ?rst block and is enabled for processing of the second block according to the mode set by the sym bits as described in t ab le 36 . 10.7 rds test modes in test mode the raw rds clock and rds data can be recovered directly from pins vafl and vafr when bit rdscda = 1. 10.8 reading rds data from the registers to read rds data the microprocessor must read byte12r to byte19r. all 8 bytes must be read to reset the status bytes 12r and 13r, i.e. effectively the status bits can be updated by the decoder after reading the last bit of byte19r. bit dovf is cleared after reading the last bit of byte19r and the status of bit sync does not depend on reading the register, bit sync indicates if the decoder is synchronized or not. when starting a read action from byte12r, the decoder blocks updates from the rds bytes until byte19r has been read. rds byte12r to byte19r must be read in one read action. 11. i 2 c-bus interface the i 2 c-bus interface is based on the i 2 c-bus speci?cation , version 2.1 january 2000, expanded by the following de?nitions. 11.1 write and read mode when writing all bytes, byte0w to byte10w can be written with one write action. table 8: i 2 c-bus fm write mode s byte 1 as byte 2 as byte n as byte 8 as p start chip address r/ w ack byte0w ack ..... ack byte6w ack stop 0010 000 0 xxxx xxxx xxxx xxxx table 9: i 2 c-bus rds write mode s byte 1 as byte 2 am byte n as byte 8 as p start chip address r/ w ack byte7w ack ..... ack byte10w non ack stop 0010 001 0 xxxx xxxx xxxx xxxx table 10: i 2 c-bus fm read mode s byte 1 as byte 2 am byte n am byte 17 nam p start chip address r/ w ack byte0r ack ..... ack byte15r non ack stop 0010 000 1 xxxx xxxx xxxx xxxx
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 32 of 64 philips semiconductors TEA5764HN fm radio + rds when the TEA5764HN is addressed by the fm radio address, the rds part (byte12r to byte27r) can be read in one read action. a read does not have to stop at byte11r. therefore, by effectively only using the rds part of the address, ignores some bytes which reduces i 2 c-bus access. 11.2 data transfer structure of the i 2 c-bus: ? slave transceiver ? subaddresses not used ? maximum low-level input voltage: v il = 0.3 v vrefdig ? minimum high-level input voltage: v ih = 0.7 v vrefdig remark: the i 2 c-bus operates at a maximum clock rate of 400 khz. it is not allowed to connect the TEA5764HN to a i 2 c-bus operating at a higher clock rate. data transfer to the ic: ? bit 7 of each byte is considered the msb and has to be transferred as the ?rst bit of the byte ? the lsb indicates the write or read action ? the data becomes valid byte-wise at the appropriate falling edge of the scl clock ? a stop condition after any byte can shorten transmission times. when writing to the transceiver by using the stop condition before completion of the whole transfer: C the remaining bytes will contain the old information C if the transfer of a byte is not completed the new bits will be used, but a new tuning cycle will not be started table 11: i 2 c-bus rds read mode s byte 1 as byte 2 am byte n am byte 17 nam p start chip address r/ w ack byte12r ack ..... ack byte27r non ack stop 0010 001 1 xxxx xxxx xxxx xxxx table 12: i 2 c-bus transfer description label de?nition s start condition byte 1 i 2 c-bus chip address (7 bits) r/ w = 0 for write action and r/ w = 1 for read action as acknowledge from slave TEA5764HN (sda is low) byte 2, etc. data byte (8 bits) p stop condition am acknowledge from master microcontroller (sda is low) nam non acknowledge from master microcontroller (sda is high) na non acknowledge (sda is high)
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 33 of 64 philips semiconductors TEA5764HN fm radio + rds to speed up rds traf?c it is possible to read all the rds data and then only write back byte intmsk to set the appropriate mask(s) again. i 2 c-bus activity: ? with bits pupd the TEA5764HN can be switched in a low current standby mode. the i 2 c-bus is then still active ? when the i 2 c-bus interface is deactivated, by making pin busenable low and without programmed standby mode, the TEA5764HN keeps its normal operation, but is isolated from the i 2 c-bus lines ? it is possible to operate the TEA5764HN with busenable hard wired to pin vrefdig, and have the bus interface always active. t f = fall time of both sda and scl signals: 20 + 0.1 c b < t f < 300 ns, where c b = total capacitance on bus line in pf. t r = rise time of both sda and scl signals: 20 + 0.1 c b < t f < 300 ns, where c b = total capacitance on bus line in pf. t hd;sta = hold time (repeated) start condition. after this period, the ?rst clock pulse is generated: > 600 ns. t high = high period of the scl clock: > 600 ns. t su;sta = setup time for a repeated start condition: > 600 ns. t hd;dat = data hold time: 300 < t hd;dat < 900 ns. remark: 300 ns lower limit is added because the asic has no internal hold time for the sda signal. t su;dat = data setup time: t su;dat > 100 ns. if asic is used in a standard mode i 2 c-bus system, t su;dat > 250 ns. t su;sto = setup time for stop condition: > 600 ns. t buf = bus free time between a stop and a start condition: > 600 ns. c b = capacitive load of one bus line: < 400 pf. t su;busen = bus enable setup time: t su;busen > 10 m s. t ho;busen = bus enable hold time: t ho:busen > 10 m s. fig 14. i 2 c-bus timing diagram p s sr p 001aac796 t hd;sta t buf t su;sta t su;dat t f t high t low t su;sto t r t hd;dat sda scl bus enable t su;busen t ho;busen
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 34 of 64 philips semiconductors TEA5764HN fm radio + rds 11.3 register map 11.4 byte description table 13: register overview byte byte name access reset value reference read write 0r intflag r 00 t ab le 14 1r 0w intmsk r/w 00 t ab le 15 2r 1w frqsetmsb r/w 80 t ab le 16 3r 2w frqsetlsb r/w 00 t ab le 17 4r 3w tnctrl1 r/w 08 t ab le 18 5r 4w tnctrl2 r/w d2 t ab le 19 6r frqchkmsb r - t ab le 20 7r frqchklsb r - t ab le 21 8r ifchk r - t ab le 22 9r levchk r - t ab le 23 10r 5w testbits r/w 00 t ab le 24 11r 6w testmode r/w 00 t ab le 25 12r rdsstat1 r - t ab le 28 13r rdsstat2 r - t ab le 29 14r rdslbmsb r - t ab le 30 15r rdslblsb r - t ab le 31 16r rdspbmsb r - t ab le 32 17r rdspblsb r - t ab le 33 18r rdsbbc r - t ab le 34 19r rdsgbc r - t ab le 35 20r 7w rdsctrl1 r/w 00 t ab le 36 21r 8w rdsctrl2 r/w 10 t ab le 37 22r 9w pausedet r/w 00 t ab le 38 23r 10w rdsbbl r/w 00 t ab le 39 24r manid1 r 50 t ab le 40 25r manid2 r 2b t ab le 41 26r chipid1 r 57 t ab le 42 27r chpid2 r 64 t ab le 43 table 14: intflag - byte0r description bit symbol access reset functional description 7 davflg r 0 1 = rds data is available 6 testbit r 0 internal use 5 lsyncfl r 0 1 = synchronization is lost 4 ifflag r 0 1 = if count is not correct
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 35 of 64 philips semiconductors TEA5764HN fm radio + rds 3 levflag r 0 continuous checking of the rssi level 1 = rssi level has dropped below (v ssl[1:0] - v hys ) during a tuning period (preset or search) 1 = rssi level has dropped below v ssl[1:0] 2 pdflag r 0 1 = pause is detected 1 frrflag r 0 1 = tuner state machine is ready 0 blflag r 0 1 = during a search the band limit has been reached or time out table 15: intmsk - byte1r and byte0w description bit symbol access reset functional description 7 davmsk r/w 0 masks bit davflg 6 - r/w 0 reserved 5 lsymsk r/w 0 masks bit lsyncfl 4 ifmsk r/w 0 masks bit ifflag 3 levmsk r/w 0 masks bit levflag 2 pdmsk r/w 0 masks bit pdflag 1 frmsk r/w 0 masks bit frrflag 0 blmsk r/w 0 masks bit blflag table 16: frqsetmsb - byte2r and byte1w description bit symbol access reset functional description 7 sud r/w 1 1 = search up 0 = search down 6 sm r/w 0 1 = search mode 0 = preset mode 5 fr13 r/w 0 pll frequency set bits; see section 8.5 4 fr12 r/w 0 3 fr11 r/w 0 2 fr10 r/w 0 1 fr09 r/w 0 0 fr08 r/w 0 table 14: intflag - byte0r description continued bit symbol access reset functional description
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 36 of 64 philips semiconductors TEA5764HN fm radio + rds table 17: frqsetlsb - byte3r and byte2w description bit symbol access reset functional description 7 fr07 r/w 0 pll frequency set bits; see section 8.5 6 fr06 r/w 0 5 fr05 r/w 0 4 fr04 r/w 0 3 fr03 r/w 0 2 fr02 r/w 0 1 fr01 r/w 0 0 fr00 r/w 0 table 18: tnctrl1 - byte4r and byte3w description bit symbol access reset functional description 7 and 6 pupd[1:0] r/w 00 power-up and power-down 00 = fm off and rds off 01 = fm on and rds off 10 = not used 11 = fm on and rds on 5 blim r/w 0 1 = japan fm band 76 mhz to 90 mhz 0 = us / europe fm band 87.5 mhz to 108 mhz 4 swpm r/w 0 1 = software port is output of frrflag 0 = swp 3 ifctc r/w 1 1 = if count time = 15.02 ms 0 = if count time = 2.02 ms 2 afm r/w 0 1 = left and right audio muted 0 = audio not muted 1 smute r/w 0 1 = soft mute on 0 = soft mute off 0 snc r/w 0 1 = stereo noise cancellation on 0 = stereo noise cancellation off table 19: tnctrl2 - byte5r and byte4w description bit symbol access reset functional description 7 mu r/w 1 1 = left and right audio hard-muted 0 = no hard mute 6 and 5 ss[1:0] r/w 10 search stop level 00 = adc3 01 = adc5 10 = adc7 11 = adc10 4 hlsi r/w 1 1 = high-side injection 0 = low-side injection
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 37 of 64 philips semiconductors TEA5764HN fm radio + rds 3 mst r/w 0 1 = forced mono 0 = stereo on 2 swp r/w 0 1 = pin swport is high 0 = pin swport is low 1 dtc r/w 1 1 = de-emphasis time constant = 50 m s 0 = de-emphasis time constant = 75 m s 0 ahlsi r/w 0 see section 8.21.3 for the functionality of this bit table 20: frqchkmsb - byte6r description bit symbol access reset functional description 7 - - - reserved 6 - - - reserved 5 pll13 r - output frequency msb 4 pll12 r - output frequency 3 pll11 r - output frequency 2 pll10 r - output frequency 1 pll09 r - output frequency 0 pll08 r - output frequency table 21: frqchklsb - byte7r description bit symbol access reset functional description 7 pll07 r - output frequency 6 pll06 r - output frequency 5 pll05 r - output frequency 4 pll04 r - output frequency 3 pll03 r - output frequency 2 pll02 r - output frequency 1 pll01 r - output frequency 0 pll00 r - output frequency lsb table 22: ifchk - byter8 description bit symbol access reset functional description 7 if6 r - if count msb 6 if5 r - if count 5 if4 r - if count 4 if3 r - if count 3 if2 r - if count 2 if1 r - if count 1 if0 r - if count lsb 0 - - - reserved table 19: tnctrl2 - byte5r and byte4w description continued bit symbol access reset functional description
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 38 of 64 philips semiconductors TEA5764HN fm radio + rds [1] this bit does not switch the radio to mono or stereo, this depends on the rf input level as shown in sections mono stereo blend or mono stereo switched in t ab le 47 . table 23: levchk - byte9r description bit symbol access reset functional description 7 lev3 r - level count msb 6 lev2 r - level count bit 5 lev1 r - level count bit 4 lev0 r - level count lsb 3 ld r - 1 = pll is locked 0 = pll is not locked 2 stereo r - 1 = pilot detected [1] 0 = no pilot detected 1 - - - reserved 0 - - - reserved table 24: testbits - byte10r and byte5w description bit symbol access reset functional description 7 lhm r/w 0 1 = left audio output is hard muted 0 = left audio output is not hard muted 6 rhm r/w 0 1 = right audio output is hard muted 0 = right audio output is not hard muted 5 rdscda r/w 0 1 = pin vafl is rds clock and pin vafr is rds data 0 = normal operation 4 lhsw r/w 0 1 = level hysteresis is large 0 = level hysteresis is small 3 trigfr r/w 0 1 = reference frequency selected pin freqin 0 = crystal as reference pin xtal 2 ldx r/w 0 1 = local dx on, - 6 db gain of lna 0 = local dx off, lna has normal gain 1 rfagc r/w 0 1 = rfagc off 0 = rfagc on 0 intctrl r/w 0 when this bit is set to logic 1 an interrupt is generated on pin intx table 25: testmode - byte11r and byte6w description bit symbol access reset functional description 7 to 5 - r/w 0 reserved 4 tm r/w 0 1 = oscillator output and programmable divider output are enabled 0 = normal operation
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 39 of 64 philips semiconductors TEA5764HN fm radio + rds 3 tb3 r/w 0 test bits: t ab le 27 describes selection of signals output to the swport when swpm = 0; when tm = 1; tb_[3:0] = 0; which effectively is an and function. 2 tb2 r/w 0 1 tb1 r/w 0 0 tb0 r/w 0 table 26: lh - rssi level hysteresis rssi adc search stop level rssi hysteresis threshold lhsw = 0 lhsw = 1 300 521 743 10 7 5 table 27: test bits (swpm = 0) tb3 tb2 tb1 tb0 swport output signal 0000 bit swp of byte4w, depending on bits swpm and swp 0001 oscillator output 32.768 khz; when tm = 1 0010lock detect bit ld 0011 stereo bit stereo 0100 programmable divider; when tm = 1 0101 pscon; see section 9.1.4.6 011057 khz clock 0111 3-state 1000 output of rds comparator 1001 reserved 1010 reserved 1011 reserved 1100 reserved table 28: rdsstat1 - byte12r description bit symbol access reset functional description 7 - - - reserved 6 to 4 blid[2:0] r - block id of last block 000 = a 001 = b 010 = c 011 = d 100 = c 101 = e 110 = invalid block e (rbds) 111 = invalid block table 25: testmode - byte11r and byte6w description continued bit symbol access reset functional description
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 40 of 64 philips semiconductors TEA5764HN fm radio + rds 3---- 2---- 1 and 0 elb[1:0] r - number of errors for last processed block 00 = no errors 01 = maximum 2 bits 10 = maximum 5 bits 11 = uncorrectable table 29: rdstat2 - byte13r description bit symbol access reset functional description 7 to 5 bpid[2:0] r - block id of previous block 000 = a 001 = b 010 = c 011 = d 100 = c 101 = e 110 = invalid block e (rbds) 111 = invalid block 4 and 3 epb[1:0] r - number of errors for previous processed block 00 = no errors 01 = maximum 2 bits 10 = maximum 5 bits 11 = uncorrectable 2 sync r - 1 = rds bitstream is synchronized 0 = not synchronized 1 rstd r - 1 = power-on reset detected 0 = no power-on reset detected 0 dovf r - 1 = data over?ow occurred during read operation 0 = normal operation table 30: rdsrlbmsb - byte14r description bit symbol access reset functional description 7 bl15 r - last rds data byte - msb 6 bl14 r - last rds data byte 5 bl13 r - last rds data byte 4 bl12 r - last rds data byte 3 bl11 r - last rds data byte table 28: rdsstat1 - byte12r description continued bit symbol access reset functional description
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 41 of 64 philips semiconductors TEA5764HN fm radio + rds 2 bl10 r - last rds data byte 1 bl9 r - last rds data byte 0 bl8 r - last rds data byte table 31: rdslblsb - byte15r description bit symbol access reset functional description 7 bl7 r - last rds data byte 6 bl6 r - last rds data byte 5 bl5 r - last rds data byte 4 bl4 r - last rds data byte 3 bl3 r - last rds data byte 2 bl2 r - last rds data byte 1 bl1 r - last rds data byte 0 bl0 r - last rds data byte - lsb table 32: rdspbmsb - byte16r description bit symbol access reset functional description 7 bp15 r - previous rds data byte - msb 6 bp14 r - previous rds data byte 5 bp13 r - previous rds data byte 4 bp12 r - previous rds data byte 3 bp11 r - previous rds data byte 2 bp10 r - previous rds data byte 1 bp9 r - previous rds data byte 0 bp8 r - previous rds data byte table 33: rdspblsb - byte17r description bit symbol access reset functional description 7 bp7 r - previous rds data byte 6 bp6 r - previous rds data byte 5 bp5 r - previous rds data byte 4 bp4 r - previous rds data byte 3 bp3 r - previous rds data byte 2 bp2 r - previous rds data byte 1 bp1 r - previous rds data byte 0 bp0 r - previous rds data byte - lsb table 30: rdsrlbmsb - byte14r description continued bit symbol access reset functional description
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 42 of 64 philips semiconductors TEA5764HN fm radio + rds table 34: rdsbbc - byte18r description bit symbol access reset functional description 7 bbc5 r - bad block count msb 6 bbc4 r - bad block count 5 bbc3 r - bad block count 4 bbc2 r - bad block count 3 bbc1 r - bad block count 2 bbc0 r - bad block count lsb 1 gbc5 r - good block count msb 0 gbc4 r - good block count table 35: rdsgbc - byte19r description bit symbol access reset functional description 7 gbc3 r - good block count 6 gbc2 r - good block count 5 gbc1 r - good block count 4 gbc0 r - good block count lsb 3 to 0 - - - reserved table 36: rdsctrl1 - byte20r and byte7w description bit symbol access reset functional description 7 nwsy r/w 0 1 = start new synchronization 0 = normal processing 6 and 5 sym[1:0] r/w 00 error correction 00 = no correction 01 = maximum 2 bits 10 = maximum 5 bits 11 = no correction 4 rbds r/w 0 1 = rbds processing mode 0 = rds processing mode 3 and 2 dac[1:0] r/w 00 rds data output mode 00 = dava 01 = davb 10 = davc 11 = not used 1 and 0 - - - reserved table 37: rdsctrl2 - byte21r and byte8w description bit symbol access reset functional description 7 to 5 - - - reserved 4 bbg4 r/w 1 bad blocks gain msb 3 bbg3 r/w 0 bad blocks gain
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 43 of 64 philips semiconductors TEA5764HN fm radio + rds 2 bbg2 r/w 0 bad blocks gain 1 bbg1 r/w 0 bad blocks gain 0 bbg0 r/w 0 bad blocks gain lsb table 38: pausedet - byte22r and byte9w description bit symbol access reset functional description 7 and 6 pt[1:0] r/w 00 pause time 00 = 20 ms 01 = 40 ms 10 = 80 ms 11 = 160 ms 5 and 4 pl[1:0] r/w 00 pause level l = r 00 = 1 khz 01 = 1.6 khz 10 = 2.5 khz 11 = 4.0 khz 3 gbl5 r/w 0 number of good blocks lose msb 2 gbl4 r/w 0 number of good blocks lose 1 gbl3 r/w 0 number of good blocks lose 0 gbl2 r/w 0 number of good blocks lose table 39: rdsbbl - byte23r and byte10w description bit symbol access reset functional description 7 gbl1 r/w 0 number of good blocks lose 6 gbl0 r/w 0 number of good blocks lose lsb 5 bbl5 r/w 0 number of bad blocks lose msb 4 bbl4 r/w 0 number of bad blocks lose 3 bbl3 r/w 0 number of bad blocks lose 2 bbl2 r/w 0 number of bad blocks lose 1 bbl1 r/w 0 number of bad blocks lose 0 bbl0 r/w 0 number of bad blocks lose lsb table 40: manid1 - byte24r description bit symbol access reset functional description 7 version3 r 0 version code msb 6 version2 r 1 version code 5 version1 r 0 version code 4 version0 r 1 version code lsb 3 manid10 r 0 manufacturer id code msb table 37: rdsctrl2 - byte21r and byte8w description continued bit symbol access reset functional description
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 44 of 64 philips semiconductors TEA5764HN fm radio + rds 2 manid9 r 0 manufacturer id code 1 manid8 r 0 manufacturer id code 0 manid7 r 0 manufacturer id code table 41: manid2 - byte25r description bit symbol access reset functional description 7 manid6 r 0 manufacturer id code 6 manid5 r 0 manufacturer id code 5 manid4 r 1 manufacturer id code 4 manid3 r 0 manufacturer id code 3 manid2 r 1 manufacturer id code 2 manid1 r 0 manufacturer id code 1 manid0 r 1 manufacturer id code lsb 0 idav r 1 1 = manufacturer id available 0 = no manufacturer id available table 42: chipid1 - byte26r description bit symbol access reset functional description 7 chip id15 r 0 chip identi?cation code msb 6 chip id14 r 1 chip identi?cation code 5 chip id13 r 0 chip identi?cation code 4 chip id12 r 1 chip identi?cation code 3 chip id11 r 0 chip identi?cation code 2 chip id10 r 1 chip identi?cation code 1 chip id9 r 1 chip identi?cation code 0 chip id8 r 1 chip identi?cation code table 43: chipid2 - byte27r description bit symbol access reset functional description 7 chip id7 r 0 chip identi?cation code 6 chip id6 r 1 chip identi?cation code 5 chip id5 r 1 chip identi?cation code 4 chip id4 r 0 chip identi?cation code 3 chip id3 r 0 chip identi?cation code 2 chip id2 r 1 chip identi?cation code 1 chip id1 r 0 chip identi?cation code 0 chip id0 r 0 chip identi?cation code lsb table 40: manid1 - byte24r description continued bit symbol access reset functional description
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 45 of 64 philips semiconductors TEA5764HN fm radio + rds 12. limiting values [1] machine model i (l = 0.75 mh, r = 10 w , c = 200 pf). [2] human body model (r = 1.5 k w , c = 100 pf). [3] charged device model (jedec standard jesd22-c101c). 13. thermal characteristics table 44: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v lo1 vco tuned circuit output 1 - 0.3 +8 v v lo2 vco tuned circuit output 2 - 0.3 +8 v v ccd digital supply voltage - 0.3 +5.5 v v cca analog supply voltage - 0.3 +8 v v i/o(n) voltage on all inputs and outputs with respect to ground - 0.3 +5.5 v t stg storage temperature - 55 +150 c t amb ambient temperature - 40 +85 c v esd electrostatic discharge voltage mm [1] - 200 +200 v hbm all pins except pillp, rfin1, rfin2 [2] - 2000 +2000 v pin pillp only [2] - 1000 +2000 v pins rfin1 and rfin2 [2] - 1500 +2000 v cdm [3] - 500 +500 v table 45: thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air 80 k/w
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 46 of 64 philips semiconductors TEA5764HN fm radio + rds 14. static characteristics table 46: characteristics the minimum and maximum values include spread due to v cca =v ccd = 2.5 v to 3.3 v and t amb = - 20 cto+85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supply voltages v cca analog supply voltage 2.5 2.7 3.3 v v ccd digital supply voltage 2.5 2.7 3.3 v v vrefdig digital reference voltage for i 2 c-bus interface on pin vrefdig 1.65 1.8 v ccd v supply currents i cca analog supply current v cca = 2.5 v to 3.3 v operating mode 12 13.7 16 ma standby mode 0 0.1 1 m a i ccd digital supply current v ccd = 2.5 v to 3.3 v operating mode 0.3 0.7 1.5 ma standby mode 1 15 22.5 m a i vrefdig digital reference supply current operating mode; v vrefdig = 1.65 v to v ccd 0 0.5 1 m a dc operating points v loopsw voltage on pin loopsw v cd3 - 0.2 - v cd3 v v cpout voltage on pin cpout 0.1 - v cd3 - 0.1 v v lo1 voltage on pin lo1 v cd3 - 0.1 - v cd3 v v lo2 voltage on pin lo2 v cd3 - 0.1 - v cd3 v v pillp voltage on pin pillp 1.09 1.37 1.65 v v tmute voltage on pin tmute v rf = 0 v, measured with respect to pin cd3 0.6 0.7 0.8 mv v vafl voltage on pin vafl f rf = 98 mhz; v rf =1mv; no modulation 800 850 940 mv v vafr voltage on pin vafr f rf = 98 mhz; v rf =1mv; no modulation 800 850 940 mv v mpxout voltage on pin mpxout f rf = 98 mhz; v rf =1mv; no modulation 830 900 950 mv v mpxin voltage on pin mpxin f rf = 98 mhz; v rf =1mv; no modulation 0.2 0.4 0.5 v v freqin voltage on pin freqin trigfr = 1 1.3 1.5 1.7 v trigfr = 0 0 0.05 0.1 v v xtal voltage on pin xtal to cd3 trigfr = 1 0.9 1.17 1.3 v trigfr = 0 0.8 1 1.2 v v rfin1 voltage on pin rfin1 420 530 680 mv v rfin2 voltage on pin rfin2 420 530 680 mv v cagc voltage on pin cagc v rf = 0 v 1 1.57 2 v
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 47 of 64 philips semiconductors TEA5764HN fm radio + rds 15. dynamic characteristics table 47: characteristics see figure 1 ; all ac values are given in rms; the minimum and maximum values include spread due to v cca =v ccd = 2.5 v to 3.3 v and t amb = - 20 c to +85 c; unless otherwise speci?ed. all rf input values are de?ned in potential difference, except when emf is explicitly stated. symbol parameter conditions min typ max unit voltage controlled oscillator f osc oscillator frequency 150 - 217 mhz reference frequency input; pin freqin r i input resistance 500 - - k w c i input capacitance 5 6 7 pf f rsn resonance frequency - 32.768 - khz d f rsn resonance frequency deviation t amb = 25 c - 20 - +20 ppm t amb = - 20 c to +85 c - 150 - +150 ppm d duty cycle square wave 30 - 70 % v ih high-level input voltage square wave 1.15 - v cc v v il low-level input voltage square wave 0 - 0.55 v c/n carrier-to-noise ratio at 10 khz - 151 - - dbc/ hz crystal oscillator 32.768 khz; pin xtal f rsn resonance frequency t amb = 25 c - 32.768 - khz d f rsn resonance frequency deviation - 20 - +20 ppm c shunt shunt capacitance - - 3.5 pf c m motional capacitance 1.5 - 3.0 ff r s series resistance - - 75 k w synthesizer programmable divider d/d prog programmable divider ratio frqsetmsb[15:8] = xx11 1111; frqsetlsb[7:0] = 1111 1110 - - 8191 frqsetmsb[15:8] = xx00 1000; frqsetlsb[7:0] = 0000 0000 2048 - - d step(prog) programmable divider step size - 1 - charge pump; pin cpout; v loopsw = 0.2 v to (v lo2 - 0.2) v; f vco > f ref divider ratio i m(sink) peak sink current 250 500 1000 na i m(source) peak source current 250 500 1000 na if counter n length - 7 - bit v sens sensitivity voltage - 5.5 15 m v n count count result for search stop 10 m v < v rf < 1 v 31 - 3c hex t period ifctc = 1 - 15625 - m s ifctc = 0 - 1953 - m s f res frequency resolution - 4096 - hz
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 48 of 64 philips semiconductors TEA5764HN fm radio + rds logic pins; pins busenable, scl and sda r i input resistance 10 - - m w v ih high-level input voltage input switching level up 0.7v vrefdig -v vrefdig + 0.3 v v il low-level input voltage input switching level down - 0.3 - 0.3v vrefdig v software programmable port; pin swport v o(max) maximum output voltage i load = 150 m av vrefdig - 0.2 -v vrefdig v v o(min) minimum output voltage i load = 150 m a 0 - 0.2 v i sink(max) maximum sink current 400 - 2000 m a i source(max) maximum source current 500 - 1100 m a i l(max) maximum leakage current v swport = 0 v to 5 v - 1.0 - +1.0 m a interrupt ?ag; pin intx; v vrefdig = 1.65 v to 1.95 v; i load(max) = 200 m a or r pu of second device connected to pin intx is 18 k w 20 % v o(max) maximum output voltage v vrefdig - 0.2 -v vrefdig v v o(min) minimum output voltage 0.130 0.215 0.4 v i pd pull-down current 500 680 1200 m a r pu pull-up resistance 14.4 18 22.5 k w t l low time one-shot pulse time 9.9 9.98 10 ms table 47: characteristics continued see figure 1 ; all ac values are given in rms; the minimum and maximum values include spread due to v cca =v ccd = 2.5 v to 3.3 v and t amb = - 20 c to +85 c; unless otherwise speci?ed. all rf input values are de?ned in potential difference, except when emf is explicitly stated. symbol parameter conditions min typ max unit table 48: fm signal channel characteristics see figure 1 ; all ac values are given in rms; the min. and max. values include spread due to v cca = v ccd = 2.5 v to 3.3 v and t amb = - 20 cto+85 c; unless otherwise speci?ed. all rf input values are de?ned in potential difference, except when emf is explicitly stated. symbol parameter conditions min typ max unit fm rf input; pins rfin1 and rfin2 r i input resistance connected to pin gndrf 75 100 125 w c i input capacitance connected to pin gndrf 2.5 4 6 pf v sens(emf) sensitivity emf value voltage f rf = 76 mhz to 108 mhz; d f = 22.5 khz; f mod = 1 khz; (s+n)/n = 26 db; tc deem =75 m s; a-weighting ?lter; b aud = 300 hz to 15 khz - 2.3 3.5 m v ip3 in in-band 3rd-order intercept point d f 1 = 200 khz; d f 2 = 400 khz; f tune = 76 mhz to 108 mhz; rf agc = off 78 87 - db m v ip3 out out-of-band 3rd-order intercept point d f 1 = 4 mhz; d f 2 = 8 mhz; f tune = 76 mhz to 108 mhz; rf agc = off 87 93 - db m v in-band agc v i(agc)(min) minimum rf agc input voltage f rf = 98 mhz; d v th(mute) / d v sens(emf) < 4 mv/db m v 55 61 67 db m v
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 49 of 64 philips semiconductors TEA5764HN fm radio + rds wideband agc v i(rf) rf input voltage f rf = 93 mhz; f rf2 = 98 mhz; v rf2 =50db m v; d v th(mute) / d v sens(emf) < 4 mv/db m v; radio tuned to 98 mhz 66 72 78 db m v if ?lter f center center frequency 215 225 235 khz b bandwidth 85 94 102 khz s selectivity f tune = 76 mhz to 108 mhz [1] high-side; d f = +200 khz 39 43 - db low-side; d f = - 200 khz 32 36 - db high-side; d f = +100 khz 8 12 - db low-side; d f = - 100 khz 8 12 - db ir image rejection f tune = 76 mhz to 108 mhz; v rf =50db m v 24 30 - db fm if level detector and mute voltage v if if voltage v rf =0 m v 1.5 1.55 1.6 v v rf =3 m v 1.6 1.61 1.7 v v if(slope) slope of if voltage level d v level / d v rf ; v rf =10 m v to 500 m v 130 170 210 mv/20db v adc(start) adc start voltage 2 3 5 m v g step step resolution gain 2 3 5 db r tmute pin tmute output resistance 280 400 520 k w fm demodulator v o output voltage v rf =1mv; l=r; d f = 22.5 khz; f mod = 1 khz; dtc = 0; b aud = 300 hz to 15 khz 55 70 75 mv r o output resistance - - 500 w i sink sink current 30 - - m a (s+n)/n maximum signal-to-noise ratio f rf = 76 mhz to 108 mhz; v rf =1mv; l=r; d f = 22.5 khz; f mod = 1 khz; tc deem =75 m s; a-weighting ?lter; b aud = 300 hz to 15 khz 54 57 - db thd total harmonic distortion v rf = 1 mv; l = r; d f = 75 khz; f mod = 1 khz; dtc = 0; a-weighting ?lter; b aud = 300 hz to 15 khz; see figure 17 - 0.4 0.9 % thd od total harmonic distortion overdrive v rf = 1 mv; l = r; d f = 100 khz; f mod = 1 khz; dtc = 0; a-weighting ?lter; b aud = 300 hz to 15 khz; see figure 17 --1% table 48: fm signal channel characteristics continued see figure 1 ; all ac values are given in rms; the min. and max. values include spread due to v cca = v ccd = 2.5 v to 3.3 v and t amb = - 20 cto+85 c; unless otherwise speci?ed. all rf input values are de?ned in potential difference, except when emf is explicitly stated. symbol parameter conditions min typ max unit
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 50 of 64 philips semiconductors TEA5764HN fm radio + rds am sup am suppression l = r; d f = 22.5 khz; f mod = 1 khz; v rf = 100 m v to 10 mv; m = 0.3; dtc = 0; b aud = 300 hz to 15 khz - 40 - - db soft mute; smute = 1; d f = 22.5 khz; f mod = 1 khz v start(mute) mute start voltage relative to v vafl at v rf = 1 mv; a mute =3db 3510 m v a mute mute attenuation v rf = 1 m v; l = r; dtc = 0; b aud = 300 hz to 15 khz 10 20 30 db mpx decoder v vafl left audio output voltage on pin vafl v rf = 1 mv; l = r; d f = 22.5 khz; f mod = 1 khz; no pre-emphasis; tc deem =75 m s 55 66 75 mv v vafr right audio output voltage on pin vafr v rf = 1 mv; l = r; d f = 22.5 khz; f mod = 1 khz; no pre-emphasis; tc deem =75 m s 55 66 75 mv r vafl output resistance on pin vafl rdscda = 0 mu = lhm = rhm = 0 50 - 100 w mu = lhm = rhm = 1 500 - - k w r vafr output resistance on pin vafr rdscda = 0 mu = lhm = rhm = 0 50 - 100 w mu = lhm = rhm = 1 500 - - k w i sink(vafl) sink current on pin vafl 200 - 300 m a i sink(vafr) sink current on pin vafr 200 - 300 m a a odi input overdrive range thd = 3 % relative to f mpx = 1 khz; v mpx = 250 mv 4- - db d v o(vafl-vafr) output voltage difference between pins vafl and vafr v rf = 1 mv; l = r; d f = 75 khz including 9 % pilot deviation; f mod = 1 khz - 0.5 - +0.5 db a cs channel separation v rf = 1 mv; d f = 75 khz including 9 % pilot deviation; r = 1; l = 0 or r = 0; l = 1; f mod = 1 khz; mst = 0; snc = 1; b aud = 300 hz to 15 khz 27 - - db f u upper 3 db bandwidth v rf = 1 mv; d f = 22.5 khz; pre-emphasis = 75 m s; dtc = 0; l = r; with c between pin 27 and pin 26 = 33 nf 5% 13 15 17 khz f l lower 3 db bandwidth 20 30 50 hz (s+n)/n(m) maximum signal-to-noise ratio, mono v rf = 1 mv; d f = 22.5 khz; l = r; f mod = 1 khz; de-emphasis = 75 m s; b af = 300 hz to 15 khz; a-weighting ?lter 54 57 - db (s+n)/n(s) maximum signal-to-noise ratio, stereo v rf = 1 mv; d f = 67.5 khz; l = r; f mod = 1 khz; d f pilot = 6.75 khz; de-emphasis = 75 m s; b af = 300 hz to 15 khz; a-weighting ?lter 50 54 - db table 48: fm signal channel characteristics continued see figure 1 ; all ac values are given in rms; the min. and max. values include spread due to v cca = v ccd = 2.5 v to 3.3 v and t amb = - 20 cto+85 c; unless otherwise speci?ed. all rf input values are de?ned in potential difference, except when emf is explicitly stated. symbol parameter conditions min typ max unit
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 51 of 64 philips semiconductors TEA5764HN fm radio + rds thd total harmonic distortion v rf =1mv;l=1;r=0; d f=75khz including 9 % pilot deviation; f mod = 1 khz; dtc = 0; b aud = 300 hz to 15 khz; a-weighting ?lter mono; l = r; no pilot deviation - 0.4 0.9 % stereo; l = 1, r = 0; 9 % pilot deviation; see figure 17 - 0.9 2.5 % a sup(pilot) pilot suppression measured at pins vafl and vafr; related to d f = 75 khz including 9 % pilot deviation; f mod = 1 khz; dtc = 0 40 50 - db d f pilot pilot frequency deviation v rf =1mv t ab le note [2] a hys(pilot) pilot tone detection hysteresis v rf =1mv 2 - 6 db tc deem de-emphasis time constant v rf =1mv dtc = 1 38 50 62 m s dtc = 0 57 75 93 m s mono stereo blend; snc = 1 v start(blend) blend start voltage a cs = 0.5 db [3] 2715 m v a cs channel separation v rf = 30 m v; d f = 75 khz including 9 % pilot deviation; r = 1 and l = 0 or r = 0 and l = 1; f mod = 1 khz; mst = 0; snc = 1 41016db mono stereo switching; d f = 75 khz including 9 % pilot deviation; f mod = 1 khz; snc = 0 a cs channel separation mst = 0; r = 1 and l = 0 or r = 0 and l= 1 v rf = 30 m v; increasing rf input level 27 33 - db v rf = 10 m v; decreasing rf input level --1db v sw switching voltage [4] 17 25 45 m v hys hysteresis [4] 3 3.5 4 db bus driven mute functions tuning mute; afm = 1 a mute(vafr) mute depth on pin vafr afm = 1 or rhm = 1; d f = 75 khz; mono; b aud = 300 hz to 15 khz; a-weighting ?lter - 60 - - db a mute(vafl) mute depth on pin vafl afm = 1 or lhm = 1; d f = 75 khz; mono; b aud = 300 hz to 15 khz; a-weighting ?lter - 60 - - db a mute mute depth on pins vafl and vafr mu = 1; d f = 75 khz; mono; b aud = 300 hz to 15 khz; a-weighting ?lter - 80 - - db table 48: fm signal channel characteristics continued see figure 1 ; all ac values are given in rms; the min. and max. values include spread due to v cca = v ccd = 2.5 v to 3.3 v and t amb = - 20 cto+85 c; unless otherwise speci?ed. all rf input values are de?ned in potential difference, except when emf is explicitly stated. symbol parameter conditions min typ max unit
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 52 of 64 philips semiconductors TEA5764HN fm radio + rds [1] low-side and high-side selectivity can be measured by changing the mixer lo injection from high-side to low-side. [2] when bit stereo is at logic 1 the frequency is between 2.5 khz and 5.8 khz; when bit stereo is at logic 0 the frequency is 0 khz. [3] with increasing input levels the radio switches gradually from mono to stereo. [4] the mono stereo switching level is the rf input level for switching from mono to stereo. rds demodulator/decoder; d f = 22.5 khz; f af = 1 khz; l = r; tc deem =50 m s; dtc = 1; sym1 = 0 and sym0 = 0; average over 2000 blocks i rds rds current i ccd current when rds is running 0.3 0.7 1.5 ma v sens rds sensitivity emf value d f = 22.5 khz; f af = 1 khz; l = r; sym1 = 0 and sym0 = 0 block quality rate 3 85 %; d f rds = 1.2 khz - 24.7 32.5 m v block quality rate 3 95 %; d f rds = 2 khz -1526 m v f center ?lter center frequency 56.5 57 57.5 khz b bandwidth 2.5 3 3.5 khz pause detector f th(det)(pause) pause detection threshold frequency f mod = 1 khz; l = r; pl0 = 0; pl1 = 0 0.7 1.0 1.4 khz table 48: fm signal channel characteristics continued see figure 1 ; all ac values are given in rms; the min. and max. values include spread due to v cca = v ccd = 2.5 v to 3.3 v and t amb = - 20 cto+85 c; unless otherwise speci?ed. all rf input values are de?ned in potential difference, except when emf is explicitly stated. symbol parameter conditions min typ max unit
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 53 of 64 philips semiconductors TEA5764HN fm radio + rds (1) mono signal, soft mute off (f fm = 22.5 khz; f af = 1 khz) (2) noise in mono mode, soft mute off (3) total harmonic distortion, d f = 75 khz (f fm = 75 khz; f af = 1 khz) v cca = 2.7 v; t amb = 25 c; af out : a-weighting ?lter, bp ?lter: 300 hz to 15 khz 0 db = 72 mv at 2 m v rf - 3 db = 0.8 m v 26 db = 1.2 m v rf = 98 mhz measurements/decade: 12 fig 15. mono characteristics 001aac797 v rf (v) 10 - 7 10 - 1 1 10 - 2 10 - 3 10 - 6 10 - 4 10 - 5 - 40 - 60 - 20 0 (db) - 80 2.0 1.0 3.0 4.0 thd, n (%) 0 (2) (3) (1)
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 54 of 64 philips semiconductors TEA5764HN fm radio + rds (1) v afl signal, soft mute off ( d f r = 67.5 khz; f af = 1 khz; d f pilot = 6.75 khz) (2) v afr signal, soft mute off ( d f l = 67.5 khz; f af = 1 khz; d f pilot = 6.75 khz) (3) noise in stereo mode, soft mute off ( d f l = 0 khz; f af = 1 khz; d f pilot = 6.75 khz) (4) total harmonic distortion, d f = 75 khz ( d f r = 67.5 khz; f af = 1 khz; d f pilot = 6.75 khz) v cca = 2.7 v; t amb = 25 c; af out : a-weighting ?lter, bp ?lter: 300 hz to 15 khz; snc = on 0 db = 233 mv at 470 m v rf 26 db = 1.1 m v rf = 98 mhz measurements/decade: 12 fig 16. stereo characteristics 001aac798 v rf (v) 10 - 7 10 - 1 1 10 - 2 10 - 3 10 - 6 10 - 4 10 - 5 - 40 - 60 - 20 0 (db) - 80 2.0 1.0 3.0 4.0 thd, n (%) 0 (2) (4) (3) (1)
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 55 of 64 philips semiconductors TEA5764HN fm radio + rds (1) mono signal, soft mute on (f fm = 22.5 khz; f af = 1 khz) (2) noise in mono mode, soft mute on (3) total harmonic distortion, d f = 100 khz (f fm = 100 khz; f af = 1 khz) v cca = 2.7 v; t amb = 25 c; af out : a-weighting ?lter, bp ?lter: 300 hz to 15 khz; soft mute on 0 db = 71 mv at 10 m v rf 26 db = 1.3 m v rf = 98 mhz measurements/decade: 12 fig 17. soft mute and overdrive characteristics fig 18. adc conversion levels 001aac799 v rf (v) 10 - 7 10 - 1 1 10 - 2 10 - 3 10 - 6 10 - 4 10 - 5 - 40 - 60 - 20 0 (db) - 80 2.0 1.0 3.0 4.0 thd, n (%) 0 (2) (3) (1) 001aac800 10 - 5 10 - 6 10 - 4 10 - 3 v rfin1 , v rfin2 (v) 10 - 7 adc output 0 16 12 48
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 56 of 64 philips semiconductors TEA5764HN fm radio + rds 16. application information table 49: list of components symbol parameter type manufacturer d1, d2 varicap diode for vco tuning bb202 philips l1 rf band ?lter coil 120 nh; q min = 20; tolerance: 5 % coilcraft; murata l2, l3 vco coil 33 nh; q min = 40; tolerance: 2 % coilcraft; murata x1 32.768 khz crystal act200; c l = 12 pf; d f/f 0 = 20 ppm; see section 15 act r 10 k w ; 47 k w ; 100 k w 10 % max c 27 pf; 47 pf; 100 pf; 12 pf; 10 nf(2 ); 33 nf(8 ) 10 % max
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 57 of 64 philips semiconductors TEA5764HN fm radio + rds 17. package outline fig 19. package outline sot618-1 (hvqfn40) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 6.1 5.9 d h 4.25 3.95 y 1 6.1 5.9 4.25 3.95 e 1 4.5 e 2 4.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot618-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot618-1 hvqfn40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 11 20 40 31 30 21 10 1 x d e c b a e 2 01-08-08 02-10-22 terminal 1 index area 1/2 e 1/2 e a c c b v m w m note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) e (1)
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 58 of 64 philips semiconductors TEA5764HN fm radio + rds 18. soldering 18.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 18.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 cto270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 18.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 59 of 64 philips semiconductors TEA5764HN fm radio + rds C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 18.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 18.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. table 50: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, vfbga, xson not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5] [6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 60 of 64 philips semiconductors TEA5764HN fm radio + rds [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages.
philips semiconductors TEA5764HN fm radio + rds TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 61 of 64 19. revision history table 51: revision history document id release date data sheet status change notice doc. number supersedes TEA5764HN_2 20050809 product data sheet - - TEA5764HN_1 modi?cations: ? speci?cation status changed from objective data sheet to product data sheet. TEA5764HN_1 20050707 objective data sheet - 9397 750 13453 -
philips semiconductors TEA5764HN fm radio + rds TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 62 of 64 20. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 21. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 22. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 23. trademarks notice all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus wordmark and logo are trademarks of koninklijke philips electronics n.v. 24. contact information for additional information, please visit: http://www.semiconductors.philips.com for sales of?ce addresses, send an email to: sales.addresses@www.semiconductors.philips.com level data sheet status [1] product status [2] [3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
philips semiconductors TEA5764HN fm radio + rds TEA5764HN_2 ? koninklijke philips electronics n.v. 2005. all rights reserved. product data sheet rev. 02 9 august 2005 63 of 64 continued >> 25. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 functional description . . . . . . . . . . . . . . . . . . . 6 8.1 low noise rf ampli?er . . . . . . . . . . . . . . . . . . 6 8.2 fm i/q mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.3 vco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.4 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . 7 8.5 pll tuning system . . . . . . . . . . . . . . . . . . . . . . 7 8.6 band limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.7 rf agc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.8 local or long distance receive . . . . . . . . . . . . . 8 8.9 if ?lter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.10 fm demodulator . . . . . . . . . . . . . . . . . . . . . . . . 8 8.11 if counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.12 voltage level generator and analog-to-digital converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.13 mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.13.1 soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.13.2 hard mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.13.3 audio frequency mute . . . . . . . . . . . . . . . . . . . . 9 8.14 mpx decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.15 signal dependent mono/stereo blend (stereo noise cancellation) . . . . . . . . . . . . . . . . . . . . . 10 8.16 software programmable port . . . . . . . . . . . . . 10 8.17 standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 10 8.18 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10 8.19 rds/rbds . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.19.1 rds/rbds demodulator . . . . . . . . . . . . . . . . 10 8.19.2 rds data and clock direct . . . . . . . . . . . . . . . 11 8.19.2.1 rds/rbds decoder . . . . . . . . . . . . . . . . . . . . 11 8.20 audio pause detector . . . . . . . . . . . . . . . . . . . 11 8.21 auto search and preset mode . . . . . . . . . . . . 11 8.21.1 search mode . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.21.2 preset mode . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.21.3 auto high-side and low-side injection stop switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.21.4 muting during search or preset . . . . . . . . . . . . 14 8.22 rds update/alternative frequency jump . . . . . 14 8.22.1 muting during rds update . . . . . . . . . . . . . . . 15 9 interrupt handling . . . . . . . . . . . . . . . . . . . . . . 16 9.1 interrupt register. . . . . . . . . . . . . . . . . . . . . . . 16 9.1.1 interrupt clearing . . . . . . . . . . . . . . . . . . . . . . 17 9.1.2 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.1.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.1.4 interrupt ?ags and behavior . . . . . . . . . . . . . . 19 9.1.4.1 multiple interrupt events . . . . . . . . . . . . . . . . . 19 9.1.4.2 data available ?ag . . . . . . . . . . . . . . . . . . . . . 19 9.1.4.3 rds synchronization ?ag. . . . . . . . . . . . . . . . 19 9.1.4.4 if frequency ?ag . . . . . . . . . . . . . . . . . . . . . . 20 9.1.4.5 rssi threshold ?ag . . . . . . . . . . . . . . . . . . . . 20 9.1.4.6 pause detection ?ag. . . . . . . . . . . . . . . . . . . . 21 9.1.4.7 frequency ready ?ag . . . . . . . . . . . . . . . . . . . 22 9.1.4.8 band limit ?ag. . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2 interrupt output. . . . . . . . . . . . . . . . . . . . . . . . 23 10 rds data processing . . . . . . . . . . . . . . . . . . . 23 10.1 dav-a processing mode. . . . . . . . . . . . . . . . . 24 10.2 dav-b processing mode / fast pi search mode 25 10.3 dav-c reduced processing mode . . . . . . . . . 26 10.4 synchronization . . . . . . . . . . . . . . . . . . . . . . . 28 10.4.1 conditions for synchronization . . . . . . . . . . . . 28 10.4.2 data over?ow . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.5 rds ?ag behavior during read action . . . . . . 30 10.6 error detection and reporting . . . . . . . . . . . . . 31 10.7 rds test modes . . . . . . . . . . . . . . . . . . . . . . . 31 10.8 reading rds data from the registers . . . . . . 31 11 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . . 31 11.1 write and read mode . . . . . . . . . . . . . . . . . . . 31 11.2 data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . 32 11.3 register map . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.4 byte description . . . . . . . . . . . . . . . . . . . . . . . 34 12 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 45 13 thermal characteristics . . . . . . . . . . . . . . . . . 45 14 static characteristics . . . . . . . . . . . . . . . . . . . 46 15 dynamic characteristics . . . . . . . . . . . . . . . . . 47 16 application information . . . . . . . . . . . . . . . . . 56 17 package outline . . . . . . . . . . . . . . . . . . . . . . . . 57 18 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 18.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 18.2 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 58 18.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 58 18.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 59 18.5 package related soldering information . . . . . . 59 19 revision history . . . . . . . . . . . . . . . . . . . . . . . 61 20 data sheet status. . . . . . . . . . . . . . . . . . . . . . . 62
? koninklijke philips electronics n.v. 2005 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 9 august 2005 document number: TEA5764HN_2 published in the netherlands philips semiconductors TEA5764HN fm radio + rds 21 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 22 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 23 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 24 contact information . . . . . . . . . . . . . . . . . . . . 62

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